The specification for the PCIe Gen3 (Peripheral Component Interconnect Express, third generation starting with version 3.0) protocol introduces 128-to-130 bit encoding. A serial stream has a 2-bit sync-header followed by a 128 bit payload known as blocks. The sync header can be either 01 or 10 in binary indicating a PCIe receiver whether the following 128-bits are a data block or an ordered set block. Ordered set blocks facilitate link training and help set the link up in order to process the data blocks. The 128 bit payload are in the form of 8 bit symbols which can be easily processed by the link and transaction layers of the PCIE receiver. However the 2 bit sync headers cannot be processed easily by the link and transactional layers so they are removed before the receiver's link layer processes incoming data blocks, the sync headers are removed.
However, removal of these 2 bit sync headers every 16 cycles of e.g. a 1 GHz clock, creates an underflow condition in the upstream data which can only be corrected by inserting an upstream dead cycle (a cycle with no data) after every 64 cycles of the 1 GHz clock of data. The dead cycles can occur at different times in each lane of a PCIe interface depending on the physical channel lengths of the PCIE lanes. The injection of dead-cycles into data transfers over the bus has the effect of causing latency in each lane of a multiple lane PCIe link. However, different lanes of the PCIe link have different amounts of latency. As a result, dead-cycle behavior is different across different lanes and this causes indeterminism.